Suppose we have a 4:5 ratio. This should look something like this: FSB clocks ........... C1F ......... C2F ........ C3F ......... C4F ____↑¯¯¯¯↓____↑¯¯¯¯↓____↑¯¯¯¯↓____↑¯¯¯¯↓ ... C1R ......... C2R ........ C3R ........ C4R ........ M1F ..... M2F ..... M3F ..... M4F ..... M5F ___↑¯¯¯↓___↑¯¯¯↓___↑¯¯¯↓___↑¯¯¯↓___↑¯¯¯↓ .. M1R ..... M2R .... M3R ..... M4R ..... M5R Memory bus clocks where: CxR = FSB rising edge of clock x after synchronization CxF = FSB falling edge of clock x after synchronization MxR = Memory bus rising edge of clock x after synchronization MxF = Memory bus falling edge of clock x after synchronization Please, can someone tell me for each rising (CxR) or falling (CxF) edge of the FSB clock --- when data is transferred from the CPU to the North Bridge Chipset, in order to be stored in Memory --- on what rising (MxR) or falling (MxF) edge of the Memory Bus clock that data will reach the Memory from the North Bridge Chipset?
well dude that's too much detail if i try to explain it you won't understand it believe me this case includes pipelining between parts. cache and pre-caching processes etc. if you still wanna learn i'm gonna tell you but a brief summery of all post a reply if you want it too much
Often times, ratios were used to keep the RAM and CPU FSB running at their native clocks for best performance. As far as memory transfers go, it depends on the type. For DRAM there are two major types: SDR and DDR Furthermore, for this explaination, the rising edge of the clock is a binary 1 (on/yes) and the falling edge is binary 0 (off/no). SDR operates by transmitting data on the rising edge of the clock. DDR doubles performance by transmitting data on both the rising and falling edge of the clock. Now, I'm no electronics major, and I slept through a lot of college classes, but as far as answering the question, for SDR it must be at the rising edge; for DDR it's either/or. I'm not sure about Rambus (RDRAM), however. I do hope this isn't a homework question....
Yes, I want to know all of it. About how the transfer of data between the CPU and Memory thru a MCH works, when using different ratios. Because I've read in an article that sometimes using faster memory doesn't increase performance.
That's going to depend on the app in use. Above 1:1 (CPU FSB:RAM) ratios, you're generally going to have diminishing returns. The idea of buying faster RAM is to either run tighter timings, overclock, and typically both. Running an FSB:RAM ratio like 4:5, where the RAM is faster can decrease performance if the timings are high enough to negate the effects of the faster speed. It's something of a balancing act. Having faster RAM allows optimal timings at a 1:1 ratio, so you can get the maximum out of the CPU without overclocking. Now, this is when a game or app works on memory bandwidth, not strictly CPU speed.
Hello Everyone. I'm new to the forum arena and I'm not very knowledgeable regarding most things computer. However, like many others who have posted in various places here, I too am heading for an upgrade. I have done my best to trawl the existing posts here and have found invaluable advice and insight (thanks to all concerned). My unanswered question is: assuming DDR2-667 to be the optimum memory for my future (not to be overclocked) 1333 FSB motherboard, would installing DDR2-800 memory actually result in a slightly degraded performance if the specs for the DDR-667 are (cl 4-4-4-12) and for the DDR2-800 are (cl 5-5-5-15)?
allright then i'll try to simplfy it as you can understand. we use higher fsb cpu's to increase data enchancement rate right? to support it system's data gate must be eligible to handle it this is like if we are using a 800mhz dual ram kit the gate will be 6.4gb/s these speeds are theorical but i've seen it reached 5.5gbps really. sometimes faster sticks will be slower because of the latency values for ex. if we have two sticks, one of them a ddr2-1200mhz with cl5, the other is ddr3-1600 with cl9, the ddr2 one will be faster and more stable than the other one why? because lower latency will result in system response time's decrease. this can be in ms, also can be ns (nano seconds) decrease but it will make the cpu load lower as process range increases. this is where pipelining is included in the case cpu process speed has to be equalised wtih the data flow rate in order to prevent data loss in applications. sometimes games make a crash by returning to desktop without any reasons. this is their reason my friend. data loss made in transfer resulted in crash.in order to decrease this crashes, my experimental oc's showed me that much higher ram frequencies keeping the cas range and cpu fsb lower gives a more stable pc on games but in order to increase the performance you got to keep the values closely tight. if you have a fsb of 1600mhz you have to make a 1.2ghz ram frequency in order to balance clearly and reduce the freezes this is as much as i can simplifiy i hope i could tell it enough some places may be difficult to understand or can sound like madness but they're true (or i have written them wrong i'll check later because i don't have much time before starting to read my microprocessor notes, fck them they made me an unsociable person
Ok, to simplify this (even further?), I think it would help me very much to understand the problem, if you'll explain what happens in the MCH? How's the transition from one frequency to another frequency made there? What are the factors that influence the transfer time thru the MCH? I hope these questions make sense ...
It's not a transfer. There's a reference clock that runs at a certain speed on the motherboard. All other clocks are somehow based off that. The chipset is designed with a particular frequency in mind, and the frequency crystal in use must conform to that. There are internal multipliers within the chipset, but that's about it in terms of transition. What can influence the MCH/Northbridge would be relegated to what BIOS settings are used with the memory.
