Hi everyone! I don't understand how PCIe buses are organised. My questions are a bit long so please bear with me. Thanks in advance! Below is my machine's result from lspci -t Q1. Is it correct to say that any PCIe device connected to a PCIe Express Root Port (0:1.0, 0:1c.[0-3] and 0.1e.0) would form a PCIe bus on its own? Well, actually this appears pretty certain to me. The real question I have is: what difference does it make when a PCIe device becomes a bus on its own? Why are those root ports even needed? -[0000:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub +-01.0-[01]----00.0 ATI Technologies Inc M56P [Radeon Mobility X1600] +-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller +-1c.0-[02]-- +-1c.1-[03]----00.0 Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection +-1c.2-[04]-- +-1c.3-[05]----00.0 Broadcom Corporation NetLink BCM5789 Gigabit Ethernet PCI Express +-1d.0 Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 +-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 +-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 +-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 +-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller +-1e.0-[06-0a]--+-05.0 Texas Instruments PCIxx12 Cardbus Controller | +-05.1 Texas Instruments PCIxx12 OHCI Compliant IEEE 1394 Host Controller | +-05.2 Texas Instruments 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) | \-05.3 Texas Instruments PCIxx12 SDA Standard Compliant SD Host Controller +-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge +-1f.2 Intel Corporation 82801GBM/GHM (ICH7 Family) SATA IDE Controller \-1f.3 Intel Corporation N10/ICH 7 Family SMBus Controller Q2. Another question I have is that - It appears to me that the Northbridge and the Southbridge, combined, are just a single PCI bus numbered with the bus ID 0. Is this correct? I am asking this because I confirmed using AIDA64 that 0:0.0 and 0:1.0 belong to the Northbridge, while the rest belong to the Southbridge. I was expecting the Northbridge and Southbridge to be quite different things, but now they appear to me as a single PCI bus. If you have little time, please just try to help me answer the questions above. They are what really bother me. The questions below are more trivial and I could afford to find out their answer later ============== Q3. The FSB is not a chip, but only a data path between the CPU and the Northbridge, am I correct? What's the connection between the Northbridge and the Southbridge? Is it invisible at PCI level? Q4. Does an independent backside bus still exist in today's modern systems since most memory accesses are actually done through the caches, making the backside bus more important than the frontside bus? If backside bus still exists, what is the function of the frontside bus apart from streaming accesses to the system memory and interrupts? Q5. I've read something about interrupt controllers, pins and lines. But the material I read is quite old. My questions is: where are todays' interrupt controllers located? Are they on PCI buses? Thanks a lot for your help!
Hi, I believe the northbridge and southbridge are on the same internal bus on a motherboard. The southbridge chip has to go thru the northbridge to talk to the processor. This page talks a bit about it and also has a chart showing the different buses on a modern motherboard. http://en.wikipedia.org/wiki/Southbridge_(computing) The link is a bit strange, copy and paste it including the last parentheses to get to the page instead of clicking it...
